Yesterday, AnandTech reported that TSMC has quietly launched a performance-enhancing version of the 7nm deep-UV DUV (N7) and 5nm EUV EUV (N5) manufacturing process. The company’s N7P and N5P technologies are designed for customers who need to make the 7 nm designs run faster or consume a slightly lower amount of power.
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TSMC’s new N7P process uses the same design rules as the N7 to optimize front-end-of-line (FEOL) and middle-end-of-line (MOL), which can increase performance by 7% or lower power by 10% at the same frequency.
It is reported that TSMC first disclosed relevant information at the VLSI seminar held in Japan this year. But it has not been widely publicized. The N7P uses proven deep ultraviolet (DUV) lithography to reduce transistor density compared to N7.
TSMC customers who require transistor density higher than approximately 18% to 20% are expected to use the N7 + N6 process technology. Among them, the N6 process technology is multi-layered by ultra-violet (EUV) lithography.
In addition, TSMC’s next major node with significant density, improved power consumption, and performance is N5 (5nm). It provides a performance-enhancing version called N5P. The technology uses FEOL and MOL optimization to increase the chip’s operating speed by 7% at the same power or 15% at the same frequency.
However, this doesn’t mean the next-gen mobile chips will be based on the 5nm process node. Seems we are still too far from this technology to become commercially available. On the other hand, the chip makers are doing their best to make the chips more powerful and consume less power.