According to foreign media reports, recently in California Los Altos the Cerebras company officially released a machine called the CS-1 supercomputer. Its core is the use of 16nm process technology and wafer size of the processor array. So, the company will 21. 5 cm*21.5 cm Silicon plate named for the WSE, which claims to be the“world’s largest” chip. Even more, WSE pioneering the use of a wafer-level integration, several transistors have reached 1. 2 trillion, the loading of the 40 million cores.
Analysts reported that high-end modern computer chips can have billions of transistors. But the WSE number of transistors won more than 1 trillion. Besides, the WSE loading of 40 million cores per second can be transmitted over 9000 million billion bytes of data. In contrast, the current PC configuration Intel i9-9900k chip can transmit 8-cores 400 billion bytes of data per second.
CS-1 Supercomputer ‘s features
The supercomputer CS-1 volume is very small. Besides, there are about 240 million cores in the Summit – the world’s fastest supercomputer. But Summit uses a traditional structure, use the heavy load of the circuit board, which weighs over 340 tons and covers an area of 520 square meters. While the CS-1 weighs is only 50 kg. In terms of energy consumption, Summit supercomputer power consumption is CS-1 1000 times. It also consumes only 15-20 kW of electricity. The maximum performance requires 1000 times the energy.
People mainly use CS-1 supercomputers for machine learning and other artificial intelligence operation. The CS-1 compiler by generating the code structure and the hardware structure is matching to improve transmission efficiency. Also, since the WSE on the core position apart they used the memory of only a few millimeters. Therefore, a circuit Board from one portion to another portion of the data stream transmission will be more than usually much faster.
This wafer-level integration of the semiconductor device made the TSMC company. The TSMC process is very sophisticated. Of course, there are many other challenges for the wafer-level integrated devices, such as data synchronization, power supply, cooling, data transmission validity, and other many problems. However, if the CS-1 can be successfully achieved commercial, then wafer-level integration of the semiconductor device will eventually prove themselves.